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| LEADER |
00981cam a2200253 7i4500 |
| 001 |
0000071693 |
| 005 |
20221012090000.0 |
| 020 |
|
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|a 9789811631993 (electronic book)
|
| 090 |
0 |
0 |
|a TK7868.L6
|b T37 2022
|
| 100 |
1 |
|
|a Taraate, Vaibbhav
|
| 245 |
1 |
0 |
|a Digital logic design using Verilog :
|b coding and RTL synthesis
|c Vaibbhav Taraate.
|
| 250 |
|
|
|a Second edition.
|
| 264 |
|
|
|a Singapore:
|b Springer,
|c 2022.
|
| 300 |
|
|
|a 1 online resource (xxv, 604 pages):
|b illustrations, text file, PDF.
|
| 336 |
|
|
|a text
|2 rdacontent
|
| 337 |
|
|
|a computer
|2 rdamedia
|
| 338 |
|
|
|a online resource
|2 rdacarrier
|
| 650 |
|
0 |
|a Logic design --
|x Data processing
|
| 650 |
|
0 |
|a Verilog (Computer hardware description language)
|
| 655 |
|
0 |
|a Electronic books
|
| 856 |
4 |
2 |
|u http://library.unisel.edu.my/web/guest/mylibrary
|
| 997 |
|
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|a Communication, Visual Art & Computing, Faculty
|b Computing, Department
|
| 998 |
|
|
|a Computer Science, Degree
|
| 999 |
|
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|a EBO0014608
|b EBOOK
|c EBOOK
|e Electronic resources
|
