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20180420090000.0 |
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080829 eng |
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|a TK7871
|b .S98 2005
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|a Syukri Othman
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|a Study on NAND gate characteristic due to CMOS scaling using layout approach
|c Syukri bin Othman.
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|a Bestari Jaya, Selangor:
|b UNISEL,
|c 2005.
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|a xi, 73 p.:
|b col. ill.;
|c 30 cm.
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|a Please login MyLib (library.unisel.edu.my/web/guest/mylibrary - click eDocument)
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|a Thesis (Bachelor of Engineering-Electronic), UNISEL, 2005
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|a Includes bibliographical references and appendix
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|a Universiti Industri Selangor
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|a NAND gate --
|x characteristics
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|a CMOS scaling
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|a Engineering, Faculty
|b Engineering, Department
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|a Electronics Engineering, Degree
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|a THE0000510
|b THESIS
|c THESIS
|e Thesis Room, Bestari Jaya
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