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20210702090000.0 |
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070709 eng |
020 |
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|a 0071588922 (pbk.)
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020 |
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|a 0071445641 (hbk.)
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020 |
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|a 9780071445641
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090 |
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|a TK7885.7
|b .N38 2006
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100 |
1 |
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|a Navabi, Zainalabedin
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245 |
1 |
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|a Verilog digital system design :
|b RT level synthesis, testbench and verification
|c Zainalabedin Navabi.
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250 |
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|a 2nd ed.
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260 |
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|a New York:
|b McGraw-Hill,
|c 2006.
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300 |
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|a xvi, 384 p.:
|b ill.;
|c 24 cm..
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501 |
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|a With CD-ROM : Verilog digital systems design / Navabi
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504 |
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|a Includes bibliographical references and index
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650 |
0 |
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|a Electronic digital computers --
|x Computer-aided design
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650 |
0 |
0 |
|a Verilog (Computer hardware description language)
|
655 |
|
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|a Electronic books
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856 |
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|u http://library.unisel.edu.my/web/guest/mylibrary
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997 |
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|a Engineering & Life Sciences, Faculty
|b Engineering, Department
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999 |
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|a 0000019501
|b BOK
|c OPEN SHELF
|e 2nd Floor, Bestari Jaya
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999 |
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|a 0000035225
|b BOK
|c OPEN SHELF
|e 2nd Floor, Bestari Jaya
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999 |
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|a CDR0000524
|b CD-ROM
|c OPEN SHELF
|e Circulation Counter, Bestari Jaya
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999 |
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|a CDR0001527
|b CD-ROM
|c OPEN SHELF
|e Circulation Counter, Bestari Jaya
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999 |
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|a EBO0005560
|b EBOOK
|c EBOOK
|e Electronic resources
|